ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Vector catch operation when Security Extensions are not implemented
Debug Registers Reference
For each bit of the DBGVCR, the vector addresses caught depends on the exception vector configuration in
the SCTLR:
whether the SCTLR.V bit is programmed for Normal or High exception vectors
for catches on the FIQ and IRQ exception vectors, on the programming of the SCTLR.VE bit.
Table C10-15 shows how the vector address that corresponds to each active bit of the DBGVCR depends on
these configuration settings:
Table C10-15 Vector catch addresses, for processors without Security Extensions
DBGVCR bit Vector catch enabled
Vector catch operation when Security Extensions are implemented
Configured exception vectors
Normal (V == 0) High (V == 1)
[7] FIQ VE == 0 0x0000001C 0xFFFF001C
VE == 1 Most recent FIQ address a
[6] IRQ VE == 0 0x00000018 0xFFFF0018
VE == 1 Most recent IRQ address a
[4] Data Abort 0x00000010 0xFFFF0010
[3] Prefetch Abort 0x0000000C 0xFFFF000C
[2] SVC 0x00000008 0xFFFF0008
[1] Undefined Instruction 0x00000004 0xFFFF0004
[0] Reset 0x00000000 0xFFFF0000
a. For more information see Vector catch debug events and vectored interrupt support on
page C3-22.
When the Security Extensions are implemented, for each bit of the DBGVCR, the vector addresses caught
depends:
On the value programmed in the appropriate Vector Base Address Register:
— the Non-secure copy of the Vector Base Address Register (VBARNS) for the Non-secure state
vector catches
— the Monitor Vector Base Address Register (MVBAR) for the Secure state vector catches on
the Monitor mode vectors
— the Secure copy of the Vector Base Address Register (VBARS) for the Secure state vector
catches on the exception vectors.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-71