ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

When used for IVA comparison the format of a DBGBVR is:
When used for Context ID comparison the format of a DBGBVR is:
Debug Registers Reference
31 2 1 0
Bits [31:2] Bits [31:2] of the value for comparison. Either IVA[31:2] or ContextID[31:2].
Bits [1:0], when register used for IVA comparison
Must be written as 0b00, otherwise the generation of Breakpoint debug events is
UNPREDICTABLE
Bits [1:0], when register used for Context ID comparison
Bits [1:0] of the value for comparison, ContextID[1:0].
If the BRP does not support Context ID comparison then bits [1:0] are UNK/SBZP.
The debug logic reset values of all bits of a DBGBVR are UNKNOWN.
C10.5.2 Breakpoint Control Registers (DBGBCR)
A Breakpoint Control Register, DBGBCR, holds control information for a breakpoint. Each DBGBCR is
associated with a DBGBVR to form a Breakpoint Register Pair (BRP). For more information about BRPs
and the possible breakpoints, see Breakpoint Value Registers (DBGBVR) on page C10-48.
The DBGBCRs are:
debug registers 80-95, at offsets 0x140-0x17C
read/write registers
when the Security Extensions are implemented, Common registers.
The format of a DBGBCR, in v7 Debug, is:
See the bit descriptions for the differences in other Debug architecture versions.
Bits [31:29,23,13:9,4:3]
Reserved, UNK/SBZP.
Breakpoint address[31:2] 0 0
31 0
Context ID[31:0]
31 29
28 24 23 22 20 19 16 15 14 13 9
UNK/
SBZP
Address
range mask
DBGBVR
(0)
Linked
meaning
UNK/SBZP
Byte addr.
(0) (0)
BRP num.
select
Security state control
8 5
4 3 2 1
Privileged mode control
Breakpoint enable
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-49
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