ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Accessing the DFAR
Virtual Memory System Architecture (VMSA)
To access the DFAR you read or write the CP15 registers with set to 0, set to c6, set to
c0, and set to 0. For example:
MRC p15,0,,c6,c0,0 ; Read CP15 Data Fault Address Register
MCR p15,0,,c6,c0,0 ; Write CP15 Data Fault Address Register
c6, Instruction Fault Address Register (IFAR)
The Instruction Fault Address Register, IFAR, holds the MVA of the faulting access that caused a
synchronous Prefetch Abort exception.
The IFAR is:
a 32-bit read/write register
accessible only in privileged modes
when the Security Extensions are implemented, a Banked register.
The format of the IFAR is:
31 0
MVA of faulting address of synchronous Prefetch Abort exception
For information about using the IFAR see Fault Status and Fault Address registers in a VMSA
implementation on page B3-48.
A debugger can write to the IFAR to restore its value.
Accessing the IFAR
To access the IFAR you read or write the CP15 registers with set to 0, set to c6, set to c0,
and set to 2. For example:
MRC p15,0,,c6,c0,2 ; Read CP15 Instruction Fault Address Register
MCR p15,0,,c6,c0,2 ; Write CP15 Instruction Fault Address Register
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-125