ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.294 VCVT (between floating-point and integer, Advanced SIMD)
This instruction converts each element in a vector from floating-point to integer, or from integer to
floating-point, and places the results in a second vector.
The vector elements must be 32-bit floating-point numbers, or 32-bit integers. Signed and unsigned integers
are distinct.
The floating-point to integer operation uses the Round towards Zero rounding mode. The integer to
floating-point operation uses the Round to Nearest rounding mode.
Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
VCVT.. ,
VCVT.. ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 D 1 1 size 1 1 Vd 0 1 1 op Q M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 D 1 1 size 1 1 Vd 0 1 1 op Q M 0 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vm == ‘1’) then UNDEFINED;
if size != ‘10’ then UNDEFINED;
to_integer = (op == ‘1’); unsigned = (op == ‘1’); esize = 32; elements = 2;
if to_integer then
round_zero = TRUE; // Variable name indicates purpose of FPToFixed() argument
else
round_nearest = TRUE; // Variable name indicates purpose of FixedToFP() argument
d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == ‘0’ then 1 else 2;
A8-576 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B