ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The format of an instruction in FPINST or FPINST2 is:
Common VFP Subarchitecture Specification
Thumb encoding
15 8 7 6 5 4 3 2 1 0 15 14 13 12 11 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 D Vn Vd cp_num N Q M 0 Vm
ARM encoding
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 D Vn Vd cp_num N Q M 0 Vm
The format is the same as the format of the issued instruction, with a number of modifications. For more
information, see VFP data-processing instructions on page A7-24. The modifications from the issued
instruction are:
In the Thumb encoding, bits [15:8] of the first halfword and bit [4] of the second halfword are
reserved. In the ARM encoding, bits [31:24, 4] are reserved:
— software must ignore these bits when reading this register, and must not modify these bits
when writing to this register
— hardware must set these bits to the values shown in the encoding diagrams, that map to the
encoding of an ARM CDP instruction with the AL (always) condition.
If the instruction is a short vector instruction:
— for the FPINST Register, the source and destination registers that reference vectors are updated
to point to the source and destination registers of the exceptional iteration. The
FPEXC.VECITR field contains the number of iterations remaining. For more information, see
Exception processing for short vector instructions on page AppxB-8.
— for the FPINST Register, the full vector must be processed by support code, using the current
vector length from the FPSCR. Source and destination registers that reference vectors are
unchanged from the issued instruction.
Both MRS register read and MSR register write instructions are provided for the FPINST and FPINST2
registers, see Accessing the VFP Common subarchitecture registers on page AppxB-22.
When an exceptional instruction is bounced to support code and placed in the FPINST Register, the
FPEXC.EX bit is set to 1. This indicates that valid information is available in the FPINST Register. In
addition. when a second issued instruction is copied to the FPINST2 Register, the FPEXC.FP2V bit is set
to 1. This indicates that valid information is available in the FPINST2 Register.
When the FPEXC.EX bit is 0, indicating the VFP is not in an asynchronous exceptional state, reads of the
FPINST and FPINST2 Registers are UNPREDICTABLE and the values returned might change.
When the FPEXC.FP2V bit is 0, indicating that no second instruction was issued, reads of the FPINST2
Register are UNPREDICTABLE and the value returned might change.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxB-21