ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug State
This is a particular case of the rules for accessing CP15 registers described in Coprocessor and Advanced
SIMD instructions in Debug state.
Note
Normally, in Monitor mode, any exception automatically clears the SCR.NS bit to 0. However an exception
while in Debug state in Monitor mode does not have any effect on the value of the SCR.NS bit.
C5.5.4 Coprocessor and Advanced SIMD instructions in Debug state
The following sections describe the coprocessor and Advanced SIMD instructions in Debug state:
Instructions for CP0 to CP13, and Advanced SIMD instructions
Instructions for CP14 and CP15 on page C5-17.
Instructions for CP0 to CP13, and Advanced SIMD instructions
This subsection describes:
Coprocessor instructions for CP0 to CP13. These include the VFP instructions.
If the Advanced SIMD extension is implemented, the instruction encodings described in Advanced
SIMD data-processing instructions on page A7-10 and Advanced SIMD element or structure
load/store instructions on page A7-27.
Access controls for these instructions are determined:
by the CPACR, see:
— c1, Coprocessor Access Control Register (CPACR) on page B3-104, for a VMSA
implementation
— c1, Coprocessor Access Control Register (CPACR) on page B4-51, for a PMSA
implementation.
additionally, if the Security Extensions are implemented, by the NSACR, see c1, Non-Secure Access
Control Register (NSACR) on page B3-110.
In v6.1 Debug and v7 Debug, in Debug state the current mode and security state define the privilege and
access controls for these instructions.
In v6 Debug, in Debug state it is IMPLEMENTATION DEFINED whether these instructions are executed using
the privilege and access controls for the current mode and security state, or using the privilege and access
controls for a privileged mode in the current security state.
C5-16 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B