ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.12.12 c0, Cache Size ID Registers (CCSIDR)
Virtual Memory System Architecture (VMSA)
The Cache Size ID Registers, CCSIDR, provide information about the architecture of the caches.
The CCSIDR registers are:
32-bit read-only registers
accessible only in privileged modes
when the Security Extensions are implemented, Common registers
introduced in ARMv7.
One CCSIDR is implemented for each cache that can be accessed by the processor. CSSELR selects which
Cache Size ID Register is accessible, see c0, Cache Size Selection Register (CSSELR) on page B3-95.
The format of a CCSIDR is:
31 30 29 28 27 13 12 3 2 0
W
T
W W
RA
B A
WT, bit [31] Indicates whether the cache level supports Write-Through, see Table B3-25.
WB, bit [30] Indicates whether the cache level supports Write-Back, see Table B3-25.
RA, bit [29] Indicates whether the cache level supports Read-Allocation, see Table B3-25.
WA, bit [28] Indicates whether the cache level supports Write-Allocation, see Table B3-25.
NumSets, bits [27:13]
NumSets Associativity LineSize
(Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number
of sets does not have to be a power of 2.
Associativity, bits [12:3]
(Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The
associativity does not have to be a power of 2.
LineSize, bits [2:0]
(Log2(Number of words in cache line)) -2. For example:
Table B3-25 WT, WB, RA and WA bit values
WT, WB, RA or WA bit value Meaning
0 Feature not supported
1 Feature supported
For a line length of 4 words: Log2(4) = 2, LineSize entry = 0.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-91