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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Deprecated <strong>and</strong> Obsolete Features<br />

D.1 Deprecated features<br />

The features described in this section are present in <strong>ARM</strong>v7 for backwards compatibility. You must avoid<br />

using them in new applications where possible. They might not be present in future versions of the <strong>ARM</strong><br />

architecture.<br />

See also Semaphore instructions on page AppxD-7, Use of the SP as a general-purpose register on<br />

page AppxD-8, <strong>and</strong> Explicit use of the PC in <strong>ARM</strong> instructions on page AppxD-9.<br />

D.1.1 VFP vector mode<br />

The use of VFP vector mode is deprecated in <strong>ARM</strong>v7. For details see Appendix F VFP Vector Operation<br />

Support.<br />

D.1.2 VFP FLDMX <strong>and</strong> FSTMX instructions<br />

The use of VLDM.64 <strong>and</strong> VSTM.64 instruction encodings with an odd immediate offset is deprecated from<br />

<strong>ARM</strong>v6. The use of their pre-UAL mnemonics FLDMX <strong>and</strong> FSTMX is deprecated, except for disassembly<br />

purposes. For details see FLDMX, FSTMX on page A8-101.<br />

D.1.3 Fast context switch extension<br />

Use of the Fast Context Switch Extension (FCSE) is deprecated from <strong>ARM</strong>v6, <strong>and</strong> in <strong>ARM</strong>v7<br />

implementation of the FCSE is optional. For details of the FCSE see Appendix E Fast Context Switch<br />

Extension (FCSE).<br />

D.1.4 Direct manipulation of the Endianness bit<br />

The use of the MSR instruction to write the Endianness bit in User mode is deprecated. Use the SETEND<br />

instruction.<br />

D.1.5 Strongly-ordered memory accesses <strong>and</strong> interrupt masks<br />

Any <strong>ARM</strong>v5 instruction that implicitly or explicitly changes the interrupt masks in the CPSR, <strong>and</strong> appears<br />

in program order after a Strongly-ordered access, waits for the Strongly-ordered memory access to<br />

complete. Dependence on this behavior is deprecated in <strong>ARM</strong>v6 <strong>and</strong> <strong>ARM</strong>v7, <strong>and</strong> code must not rely on<br />

this behavior. Use an explicit memory barrier instead. For details see Strongly-ordered memory on<br />

page A3-34.<br />

D.1.6 Unaligned exception returns<br />

<strong>ARM</strong> deprecates any dependence on the requirements that the hardware ignores bits of the address<br />

transferred to the PC on an exception return. See Alignment of exception returns on page B1-39.<br />

AppxD-2 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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