ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.289 VCLT (register)
VCLT is a pseudo-instruction, equivalent to a VCGT instruction with the operands reversed. For details see
VCGT (register) on page A8-560.
A8.6.290 VCLT (immediate #0)
VCLT #0 (Vector Compare Less Than Zero) take each element in a vector, and compares it with zero. If it is
less than zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to
all zeros.
The operand vector elements can be any one of:
8-bit, 16-bit, or 32-bit signed integers
32-bit floating-point numbers.
The result vector elements are bitfields the same size as the operand vector elements.
Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
VCLT. , , #0
VCLT. , , #0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 D 1 1 size 0 1 Vd 0 F 1 0 0 Q M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 1 0 0 Q M 0 Vm
if size == ‘11’ || (F == ‘1’ && size != ‘10’) then UNDEFINED;
if Q == ‘1’ && (Vd == ‘1’ || Vm == ‘1’) then UNDEFINED;
floating_point = (F == ‘1’);
esize = 8