ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Any implementation of hardware management of the access flag must ensure that any software changes to
the translation table are not lost. The architecture does not require software that performs translation table
changes to use interlocked operations. The hardware management mechanisms for the access flag must
prevent any loss of data written to translation table entries that might occur when, for example, a write by
another processor occurs between the read and write phases of a translation table walk that updates the
access flag.
An implementation that provides hardware management of the access flag:
does not generate Access Flag faults when the access flag is enabled
uses the HW access flag field, ID_MMFR2[31:28], to indicate this implementation choice, see c0,
Memory Model Feature Register 2 (ID_MMFR2) on page B5-14.
Architecturally, an operating system that makes use of the access flag must support the software faulting
option that uses the Access Flag fault. This provides compatibility between systems that include a hardware
implementation of the access flag and those systems that do not implement this feature.
When an implementation provides hardware management of the access flag it must also implement the
SCTLR.HA bit, that can be used to enable or disable the access flag mechanism. See c1, System Control
Register (SCTLR) on page B3-96.
Changing the access flag enable
It is UNPREDICTABLE whether the TLB caches the effect of the SCTLR.AFE bit on translation tables. This
means that, after changing the SCTLR.AFE bit software must invalidate the TLB before it relies on the
effect of the new value of the SCTLR.AFE bit.
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