ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Events
One set for exceptions taken in the Secure exception modes other than Monitor mode. These are
called the Secure Local vector addresses.
One set for exceptions taken in Monitor mode. These are called the Monitor vector addresses.
You enable vector catch independently for each of these vector addresses, by setting a bit in the DBGVCR
to 1, see Vector Catch Register (DBGVCR) on page C10-67.
If the Security Extensions are not implemented, the debug logic determines whether to generate a Vector
Catch debug event by comparing every instruction fetch with the Local vector addresses.
If the Security Extensions are implemented, the debug logic determines whether to generate a Vector Catch
debug event by comparing every Secure instruction fetch with the Secure Local and Monitor vector
addresses, and by comparing every Non-secure instruction fetch with the Non-secure Local vector
addresses.
Note
Any instruction fetched from an exception vector address and committed for execution triggers a Vector
Catch debug event if the appropriate bit in the DBGVCR is set to 1. Testing for possible Vector Catch debug
events does not check whether the instruction is executed as a result of an exception entry.
Whether a Vector Catch debug event is generated for an instruction is UNPREDICTABLE if either:
The exception vector address is word-aligned and one of the following applies:
— the first unit of the instruction is in the word at the exception vector address but is not at the
exception vector address
— the first unit of the instruction is not in the word at the exception vector address but another
unit of the instruction is in that word.
This can occur when the processor is executing a variable-length instruction set, that is, in Thumb,
ThumbEE or Jazelle state.
The exception vector address is not word-aligned but is halfword-aligned and one of the following
applies:
— The first unit of the instruction is in the halfword at the exception vector address but is not at
the exception vector address. This can occur only in Jazelle state, where instructions consist
of one or more byte-sized units.
— The first unit of the instruction includes the halfword at the exception vector address but is not
at the exception vector address. This can occur only in ARM state, where all instructions are
a single word and are word-aligned.
— The first unit of the instruction is not in the halfword at the exception vector address but
another unit of the instruction is in that halfword. This can occur in variable-length instruction
set states, that is, in Thumb, ThumbEE or Jazelle state.
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