ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
Instruction Details
VMVN.dt> , # Encoding T1 / A1, Q = 1
VMVN.dt> , # Encoding T1 / A1, Q = 0
where:
See Standard assembler syntax fields on page A8-7. An ARM VMVN instruction must be
unconditional.
The data type. It must be either I16 or I32.
The destination register for a quadword operation.
The destination register for a doubleword operation.
A constant of the specified type.
See One register and a modified immediate value on page A7-21 for the range of constants available, and
the encoding of and .
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
D[d+r] = NOT(imm64);
Exceptions
Undefined Instruction.
Pseudo-instructions
One register and a modified immediate value on page A7-21 describes pseudo-instructions with a
combination of and that is not supported by hardware, but that generates the same destination
register value as a different combination that is supported by hardware.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-669