ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The Instruction Sets
Table A4-16 Advanced SIMD parallel add and subtract instructions (continued)
Instruction See
Vector Subtract VSUB (integer) on page A8-788
VSUB (floating-point) on page A8-790
Vector Subtract and Narrow, returning High Half VSUBHN on page A8-792
Vector Subtract Long, Vector Subtract Wide VSUBL, VSUBW on page A8-794
A4.13.2 Bitwise Advanced SIMD data-processing instructions
Table A4-17 shows bitwise Advanced SIMD data-processing instructions. These operate on the doubleword
(64-bit) or quadword (128-bit) extension registers, and there is no division into vector elements.
Table A4-17 Bitwise Advanced SIMD data-processing instructions
Instruction See
Vector Bitwise AND VAND (register) on page A8-544
Vector Bitwise Bit Clear (AND complement) VBIC (immediate) on page A8-546
VBIC (register) on page A8-548
Vector Bitwise Exclusive OR VEOR on page A8-596
Vector Bitwise Insert if False
Vector Bitwise Insert if True
VBIF, VBIT, VBSL on page A8-550
Vector Bitwise Move VMOV (immediate) on page A8-640
VMOV (register) on page A8-642
Vector Bitwise NOT VMVN (immediate) on page A8-668
VMVN (register) on page A8-670
Vector Bitwise OR VORR (immediate) on page A8-678
VORR (register) on page A8-680
Vector Bitwise OR NOT VORN (register) on page A8-676
Vector Bitwise Select VBIF, VBIT, VBSL on page A8-550
A4-32 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B