ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
Is a list of one or more registers to be stored, separated by commas and surrounded by
{ and }. The lowest-numbered register is stored to the lowest memory address, through to
the highest-numbered register to the highest memory address.
Encoding T2 does not support a list containing only one register. If an STM instruction with
just one register in the list is assembled to Thumb and encoding T1 is not available, it
is assembled to the equivalent STR ,[]{,#4} instruction.
The SP and PC can be in the list in ARM code, but not in Thumb code. However, ARM
instructions that include the SP or the PC in the list are deprecated.
Encoding T2 is not available for instructions with the base register in the list and ! specified,
and the use of such instructions is deprecated. If the base register is not the lowest-numbered
register in the list, such an instruction stores an UNKNOWN value for the base register.
STMEA and STMIA are pseudo-instructions for STM. STMEA refers to its use for pushing data onto Empty
Ascending stacks.
The pre-UAL syntaxes STMIA and STMEA are equivalent to STM.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); NullCheckIfThumbEE(n);
address = R[n];
for i = 0 to 14
if registers == ‘1’ then
if i == n && wback && i != LowestSetBit(registers) then
MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
else
MemA[address,4] = R[i];
address = address + 4;
if registers == ‘1’ then // Only possible for encoding A1
MemA[address,4] = PCStoreValue();
if wback then R[n] = R[n] + 4*BitCount(registers);
Exceptions
Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-375