ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
Table C6-19 Debug and management register access for separate debug and core power domains a
Core logic
powered?
Conditions Registers:
Sticky
power-down
OS
Lock
DBGDIDR,
DBGECR,
DBGDRCR
Other
debug b, d Managementc, d Reserved d
No X X OK Error OK UNP
Yes 0 0 OK OK OK OK
Yes 0 1 OK Error OK UNP
Yes 1 X OK Error OK UNP
a. See Meanings of terms and abbreviations used in this section on page C6-46 when using this table.
b. Registers in the memory region 0x000 - 0x1FC, except for the DBGDIDR, DBGECR, and DBGDRCR, and reserved
locations.
c. Registers in the memory region 0xD00 - 0xFFC, except for IMPLEMENTATION DEFINED registers.
d. For details of the behavior of accesses to reserved and IMPLEMENTATION DEFINED registers see Access to
implementation defined and reserved registers on page C6-29.
Table C6-20 OS Save and Restore and Power-down register access for separate debug and
core power domains a
Core logic
powered?
Conditions Registers:
Sticky
power-down
OS Lock
DBGOSLSR b
DBGPRCR,
DBGPRSR
DBGOSLAR b DBGOSSRR b
No X X OK UNP UNP
Yes 0 0 OK OK UNP
Yes 0 1 OK OK OK
Yes 1 X OK OK UNP
a. See Meanings of terms and abbreviations used in this section on page C6-46 when using this table.
b. If the OS Save and Restore mechanism is not implemented, these registers behave as reserved locations.
For details of the behavior of accesses to reserved and IMPLEMENTATION DEFINED registers see Access
to implementation defined and reserved registers on page C6-29.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-49