ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
SWP must be word-aligned, otherwise the instruction generates an abort. From
ARMv6, use of the SWP instruction is deprecated.
All multi-word load/store instructions must be word-aligned, otherwise the
instruction generates an abort.
Unaligned access support only applies to Normal memory. Unaligned accesses to
Strongly-ordered or Device memory are UNPREDICTABLE.
In both configurations, setting the SCTLR.A bit forces an abort on an unaligned access.
Note
In ARMv7, SCTLR.U is always set to 1. ARMv7 alignment support is the same as ARMv6K in this
configuration.
In common with ARMv7, all instruction fetches must be aligned.
G.3.2 Endian support
ARMv6 supports the same Big Endian (BE) and Little Endian (LE) support model as ARMv7, see Endian
support on page A3-7. It is IMPLEMENTATION DEFINED if the legacy big endian model (BE-32) defined for
ARMv4 and ARMv5 is also supported. For more information about BE-32 see Endian support on
page AppxH-7.
For configuration and control information, see Endian configuration and control on page AppxG-20.
BE-32 DBGWCR Byte address select values
Using the BE-32 endian model changes the meaning of the Byte address select values in DBGWCR[8:5],
described in Watchpoint Control Registers (DBGWCR) on page C10-61. When using BE-32 endianness, use
Table G-1 to interpret these values. Do not use Table C10-13 on page C10-65.
Table G-1 Byte address select values, word-aligned address, ARMv6 BE-32 endianness
DBGWCR[8:5] value Description
0000 Watchpoint never hits
xxx1 Watchpoint hits if byte at address DBGWVR:’11’ is accessed
xx1x Watchpoint hits if byte at address DBGWVR:’10’ is accessed
x1xx Watchpoint hits if byte at address DBGWVR:’01’ is accessed
1xxx Watchpoint hits if byte at address DBGWVR:’00’ is accessed
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-7