ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
The Baseline CP14 instructions are not affected by:
Debug Register Interfaces
the recommended Debug Software Enable control in the Debug Access Port, see Permissions in
relation to locks on page C6-27
the Sticky Power-down status bit in the Device Power-down and Reset Status Register (DBGPRSR),
see Device Power-down and Reset Status Register (DBGPRSR), v7 Debug only on page C10-34.
For more information on access permissions and restrictions see Access permissions on page C6-26.
In addition:
Table C6-9 Access to Baseline CP14 debug registers in v7 Debug
Conditions
Debug state Processor mode DBGDSCR.UDCCdis b
OS Lock
Yes X X 0 Proceed
Baseline CP14
instructions a
Yes X X 1 UNPREDICTABLE c
No User 0 0 Proceed
No User 0 1 UNPREDICTABLE c
No User 1 X UNDEFINED d
No Privileged X 0 Proceed
No Privileged X 1 UNPREDICTABLE c
a. Read DBGDIDR, DBGDSAR, DBGDRAR, DBGDSCRint, DBGDTRRXint, or write DBGDTRTXint.
Attempting to use an MCR instruction to read DBGDIDR, DBGDSAR, DBGDRAR, or DBGDSCRint is
UNPREDICTABLE, except in the case shown by footnote d.
b. DCC user accesses disable bit, see Debug Status and Control Register (DBGDSCR) on page C10-10.
c. Apart from reads of DBGDIDR, which proceed.
d. Under these conditions, attempting to use an MCR instruction to read DBGDIDR, DBGDSAR,
DBGDRAR, or DBGDSCRint always causes an Undefined Instruction exception.
if the debug power domain is powered down, instructions that access the debug registers are
UNPREDICTABLE
when the processor is in debug logic reset, reads of the debug registers return UNKNOWN values.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-37