ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
V. {,} , Encoded as Q = 1
V. {,} , Encoded as Q = 0
where:
Must be one of:
MAX encoded as op = 0
MIN encoded as op = 1.
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VMAX or VMIN
instruction must be unconditional.
The data types for the elements of the vectors. It must be one of:
S8 size = 0b00, U = 0
S16 size = 0b01, U = 0
S32 size = 0b10, U = 0
U8 size = 0b00, U = 1
U16 size = 0b01, U = 1
U32 size = 0b10, U = 1.
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
op1 = Int(Elem[D[n+r],e,esize], unsigned);
op2 = Int(Elem[D[m+r],e,esize], unsigned);
result = if maximum then Max(op1,op2) else Min(op1,op2);
Elem[D[d+r],e,esize] = result;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-631