ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.369 VQSUB
Vector Saturating Subtract subtracts the elements of the second operand vector from the corresponding
elements of the first operand vector, and places the results in the destination vector. Signed and unsigned
operations are distinct.
The operand and result elements must all be the same type, and can be any one of:
8-bit, 16-bit, 32-bit, or 64-bit signed integers
8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.
If any of the results overflow, they are saturated. The cumulative saturation flag, QC, is set if saturation
occurs. For details see Pseudocode details of saturation on page A2-9.
Encoding T1 / A1 Advanced SIMD
VQSUB. , ,
VQSUB. , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 0 D size Vn Vd 0 0 1 0 N Q M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 1 0 N Q M 1 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;
unsigned = (U == ‘1’);
esize = 8