ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Unallocated CP15 encodings
Protected Memory System Architecture (PMSA)
When MCR and MRC instructions perform CP15 operations, the value for the instruction is the major
register specifier for the CP15 space. Accesses to unallocated major registers are UNDEFINED. For the
ARMv7-R Architecture, this means that accesses with = {c2-c4, c8, c10, c12, c14} are UNDEFINED.
In an allocated CP15 major register specifier, MCR and MRC accesses to all unallocated encodings are
UNPREDICTABLE for privileged accesses. For the ARMv7-A architecture this means that privileged MCR and
MRC accesses with != {c2-c4, c8, c10, c12, c14} but with an unallocated combination of ,
and values, are UNPREDICTABLE. For != {c2-c4, c8, c10, c12, c14}, Figure B4-3 on page B4-23
shows all allocated allocations of , and . A privileged access using any combination not
show in the figure is UNPREDICTABLE.
Note
As shown in Figure B4-3 on page B4-23, accesses to unallocated principal ID registers map onto the Main
ID Register. These are accesses with = c0, =0, = c0, and = {4, 6, 7}.
Rules for MCR and MRC accesses to CP15 registers
All MCR operations from the PC are UNPREDICTABLE for all coprocessors, including for CP15.
All MRC operations to APSR_nzcv are UNPREDICTABLE for CP15.
The following accesses are UNPREDICTABLE:
an MCR access to an encoding for which no write behavior is defined in any circumstances
an MRC access to an encoding for which no read behavior is defined in any circumstances.
Except for CP15 encoding that are accessible in User mode, all MCR and MRC accesses from User mode are
UNDEFINED. This applies to all User mode accesses to unallocated CP15 encodings. Individual register
descriptions, and the summaries of the CP15 major registers, show the CP15 encodings that are accessible
in User mode.
Some individual registers can be made inaccessible by setting configuration bits, possibly including
IMPLEMENTATION DEFINED configuration bits, to disable access to the register. The effects of the
architecturally-defined configuration bits are defined individually in this manual. Typically, setting a
configuration bit to disable access to a register results in the register becoming UNDEFINED for MRC and MCR
accesses.
Reset behavior of CP15 registers
After a reset, only a limited subset of the processor state is guaranteed to be set to defined values. On reset,
the PMSAv7 architecture requires that the following CP15 registers are set to defined values:
the SCTLR, see c1, System Control Register (SCTLR) on page B4-45
the CPACR, see c1, Coprocessor Access Control Register (CPACR) on page B4-51
the DRSR, see c6, Data Region Size and Enable Register (DRSR) on page B4-62
the IRSR, if implemented, see c6, Instruction Region Size and Enable Register (IRSR) on page B4-63.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-27