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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Debug Events<br />

C3.1 About debug events<br />

A debug event can be either:<br />

A Software debug event, see Software debug events on page C3-5<br />

A Halting debug event, see Halting debug events on page C3-38.<br />

A processor responds to a debug event in one of the following ways:<br />

ignores the debug event<br />

takes a debug exception, see Chapter C4 Debug Exceptions<br />

enters Debug state, see Chapter C5 Debug State.<br />

The response depends on the configuration. This is shown in Table C3-1 <strong>and</strong> in:<br />

Figure C3-1 on page C3-3 for v7 Debug<br />

Figure C3-2 on page C3-4 for v6 Debug <strong>and</strong> v6.1 Debug.<br />

Configuration Behavior, for specified debug event<br />

Enabled<br />

<strong>and</strong><br />

permitted a<br />

DBGDSCR<br />

[15:14] b<br />

BKPT<br />

Instruction<br />

debug event<br />

No xx c Debug<br />

exception d<br />

Yes 00 Debug<br />

exception d<br />

Yes x1 Debug state<br />

entry<br />

Yes 10 Debug<br />

exception<br />

Other Software<br />

debug event<br />

Table C3-1 Processor behavior on debug events<br />

Halting debug<br />

event<br />

Debug-mode<br />

selected <strong>and</strong><br />

enabled<br />

Ignore Ignore e Disabled or<br />

not permitted<br />

Ignore Debug state entry f None<br />

Debug state entry Debug state entry Halting<br />

Debug exception or<br />

UNPREDICTABLE g<br />

Debug state entry f Monitor<br />

a. Invasive debug is enabled <strong>and</strong> the debug event is permitted. Whether a debug event is permitted might depend on the<br />

type of debug event as well as the configuration of the processor, see Chapter C2 Invasive Debug Authentication.<br />

b. See Debug Status <strong>and</strong> Control Register (DBGDSCR) on page C10-10.<br />

c. The value of DBGSCR[15:14] is ignored when invasive debug is disabled or the debug event is not permitted. If debug<br />

is disabled these bits are RAZ.<br />

d. When debug is disabled or the debug event is not permitted, the BKPT instruction generates a debug exception rather than<br />

being ignored. The DBGDSCR, IFSR <strong>and</strong> IFAR are set as if a BKPT Instruction debug exception occurred. See Effects<br />

of debug exceptions on CP15 registers <strong>and</strong> the DBGWFAR on page C4-4.<br />

e. The processor might enter Debug state later, see Halting debug events on page C3-38.<br />

f. In v6 Debug, it is IMPLEMENTATION DEFINED whether the processor enters Debug state or ignores the event.<br />

g. Be careful when programming debug events when Monitor debug-mode is selected <strong>and</strong> enabled, because certain<br />

conditions can lead to UNPREDICTABLE behavior, see Unpredictable behavior on Software debug events on page C3-24.<br />

In v6 Debug <strong>and</strong> v6.1 Debug, some events are ignored in this state.<br />

C3-2 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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