ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
B5.2 The CPUID registers
The CPUID registers are described in detail in the following sections:
CP15 c0, Processor Feature registers
c0, Debug Feature Register 0 (ID_DFR0) on page B5-6
c0, Auxiliary Feature Register 0 (ID_AFR0) on page B5-8
CP15 c0, Memory Model Feature registers on page B5-9
CP15 c0, Instruction Set Attribute registers on page B5-19.
See also General features of the CPUID registers on page B5-3.
B5.2.1 CP15 c0, Processor Feature registers
The Processor Feature registers, ID_PFR0 and ID_PFR1, provide information about the instruction set state
support and programmers’ model for the processor. There are two Processor Feature registers, described in:
c0, Processor Feature Register 0 (ID_PFR0)
c0, Processor Feature Register 1 (ID_PFR1) on page B5-5
Accessing the Processor Feature registers on page B5-6.
c0, Processor Feature Register 0 (ID_PFR0)
The format of ID_PFR0 is:
31 16 15 12 11 8 7 4 3 0
Bits [31:16] Reserved, RAZ.
State3, bits [15:12]
State2, bits [11:8]
Reserved, RAZ
ThumbEE instruction set support. Permitted values are:
0b0000 Not supported.
0b0001 ThumbEE instruction set supported.
The value of 0b0001 is only permitted when State1 == 0b0011.
State3 State2 State1 State0
Jazelle extension support. Permitted values are:
0b0000 Not supported.
0b0001 Support for Jazelle extension, without clearing of JOSCR.CV on exception
entry.
0b0010 Support for Jazelle extension, with clearing of JOSCR.CV on exception entry.
B5-4 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B