ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
ARMv6 defines a standard set of cache operations for level 1 instruction, data, and unified caches. The cache
operations required are:
for an instruction cache:
— invalidate all entries
— invalidate entries by Modified Virtual Address (MVA)
— invalidate entries by set/way
for a data cache:
— invalidate all entries, clean all entries
— invalidate entries by MVA, clean entries by MVA
— invalidate entries by set/way, clean entries by set/way
for a unified cache:
— invalidate all entries
— invalidate entries by MVA, clean entries by MVA
— invalidate entries by set/way, clean entries by set/way
Note
In ARMv7:
cache operations are defined as affecting the caches when the caches are disabled.
address based cache maintenance operations are defined as affecting all memory types.
Before ARMv7 these features of the cache operations are IMPLEMENTATION DEFINED.
ARMv6 defines a number of optional cache range operations. The defined range operations are:
for an instruction cache:
— invalidate range by VA
for a data cache:
— invalidate range by VA
— clean range by VA
— clean and invalidate range by VA
prefetch related operations:
— prefetch instruction range by VA
— prefetch data range by VA
— stop prefetch range.
For more information, see Block transfer operations on page AppxG-41.
CP15 also supports configuration and control of cache lockdown. For details of the CP15 cache operation
and lockdown support in ARMv6, see:
c7, Cache operations on page AppxG-38
c9, Cache lockdown support on page AppxG-45.
AppxG-22 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B