ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register In a Description, see
Register Index
IRACR PMSA c6, Instruction Region Access Control Register (IRACR) on page B4-65
IRBAR PMSA c6, Instruction Region Base Address Register (IRBAR) on page B4-61
IRSR PMSA c6, Instruction Region Size and Enable Register (IRSR) on page B4-63
ISETSTATE ISETSTATE on page A2-15
ISR VMSA c12, Interrupt Status Register (ISR) on page B3-150
ITCM-NSACR, ARMv6 c9, TCM Non-Secure Access Control Registers, DTCM-NSACR and
ITCM-NSACR on page AppxG-51
ITCMRR, ARMv6 c9, TCM Region Registers (DTCMRR and ITCMRR) on page AppxG-47
ITLBIALL VMSA CP15 c8, TLB maintenance operations on page B3-138
ITLBIASID VMSA CP15 c8, TLB maintenance operations on page B3-138
ITLBIMVA VMSA CP15 c8, TLB maintenance operations on page B3-138
ITLBLR, pre-ARMv7 c10, VMSA TLB lockdown support on page AppxH-59
ITSTATE ITSTATE on page A2-17
Jazelle ID Jazelle ID Register (JIDR) on page A2-76
Jazelle Main Configuration Jazelle Main Configuration Register (JMCR) on page A2-77
Jazelle OS Control Jazelle OS Control Register (JOSCR) on page B1-77
JIDR Jazelle ID Register (JIDR) on page A2-76
JMCR Jazelle Main Configuration Register (JMCR) on page A2-77
JOSCR Jazelle OS Control Register (JOSCR) on page B1-77
Lock Access Lock Access Register (DBGLAR) on page C10-94
Lock Status Lock Status Register (DBGLSR) on page C10-95
LR ARM core registers on page A2-11 for application-level description
ARM core registers on page B1-9 for system-level description
LR_abt, LR_fiq, LR_irq, LR_mon,
LR-_svc, LR-_und, LR_usr
ARM core registers on page B1-9
Table K-1 Register index (continued)
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxK-15