ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug State
3. The processor signals that it has entered Debug state and is ready for an external agent to take control:
the DBGDSCR.HALTED bit is set to 1
the DBGDSCR.MOE field is set according to Table C10-3 on page C10-26.
For details of the recommended external debug interface, see Run-control and cross-triggering signals on
page AppxA-5 and DBGACK and DBGCPUDONE on page AppxA-7.
C5.2.1 Effect of entering Debug state on CP15 registers and the DBGWFAR
The actions taken on entering Debug state depend on what caused the Debug state entry:
If Debug state was entered following a Watchpoint debug event, then the DBGWFAR is updated with
the Instruction Virtual Address (IVA) of the instruction that accessed the watchpointed address, plus
an offset that depends on the instruction set state of the processor when the debug event was
generated:
— 8 in ARM state
— 4 in Thumb and ThumbEE states
— IMPLEMENTATION DEFINED in Jazelle state.
See Memory addresses on page C3-23 for a definition of the IVA used to update the DBGWFAR.
Otherwise, the DBGWFAR is unchanged on entry to Debug state.
Note
The implementation of the DBGWFAR depends on the Debug architecture version:
— In v6 Debug it is implemented as a register in CP15 c6.
— In v6.1 Debug it is implemented in CP14, and use of the CP15 alias is deprecated.
— In v7 Debug it can be implemented in the Extended CP14 interface, and has no alias in CP15.
For more information, see Watchpoint Fault Address Register (DBGWFAR) on page C10-28.
In all cases, on Debug state entry the DBGWFAR is set as described in this section.
In ARMv7, all CP15 registers are unchanged on entry to Debug state. In ARMv6, all CP15 registers except
for the DBGWFAR are unchanged on entry to Debug state. The unchanged registers include the IFSR,
DFSR, DFAR, and IFAR.
On a processor that implements the Security Extensions, the SCR.NS bit is not changed on entry to Debug
state.
C5-4 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B