ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

TLB lockdown procedure, using the by entry model
ARMv4 and ARMv5 Differences
The normal procedure for locking down N TLB entries where the Base field can be modified is as follows:
1. Ensure that no processor exceptions can occur during the execution of this procedure, for example by
disabling interrupts.
2. If an instruction TLB or unified TLB is being locked down, write the appropriate version of
register c10 with Base == N, Victim == N, and P == 0. If appropriate, turn off facilities like branch
prediction that make instruction prefetching harder to understand.
3. Invalidate the entire TLB to be locked down.
4. If an instruction TLB is being locked down, ensure that all TLB entries are loaded that relate to any
instruction that could be prefetched by the rest of the lockdown procedure. Provided care is taken
about where the lockdown procedure starts, one TLB entry can usually cover all of these. This means
that the first instruction prefetch after the TLB is invalidated can do this job.
If a data TLB is being locked down, ensure that all TLB entries are loaded that relate to any data
accessed by the rest of the lockdown procedure, including any inline literals used by its code. Usually
the best way to do this is to avoid using inline literals in the lockdown procedure, and to put all other
data used by it in an area covered by a single TLB entry, and then to load one data item.
If a unified TLB is being locked down, do both of the above.
5. For each of value of i from 0 to N-1:
a. Write to the CP15 c10 register with Base == i, Victim == i, and P == 1.
b. Force a translation table walk to occur for the area of memory whose translation table walk
result is to be locked into TLB entry i as follows:
If a data TLB or unified TLB is being locked down, load an item of data from the area
of memory.
If an instruction TLB is being locked down, use the CP15 c7 prefetch instruction cache
line operation defined in Table H-21 on page AppxH-49 to prefetch an instruction from
the area of memory.
6. Write to the CP15 c10 register with Base == N, Victim == N, and P == 0.
Note
If the FCSE is being used, care is required in step 5b because:
If a data TLB or a unified TLB is being locked down, the address used for the load instruction is
subject to modification by the FCSE.
If an instruction TLB is being locked down, the address used for the CP15 c7 operation is being
treated as data and so is not subject to modification by the FCSE.
To minimize the possible confusion caused by this, ARM recommends that the lockdown procedure:
starts by disabling the FCSE, by setting the PID to zero
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-61