ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Note
The conditions for setting ADABORT_l to 1 are different in v7 Debug and
v6.1 Debug. For more information, see the description of the ADABORT_l bit,
bit [7].
It is IMPLEMENTATION DEFINED whether the hardware automatically sets this bit to 1 on
entry to Debug state, see Asynchronous aborts and entry to Debug state on page C5-5.
The processor clears this bit to 0 on exit from Debug state.
NS, bit [18], v6.1 Debug and v7 Debug
Non-secure state status bit. If the processor implements Security Extensions, this bit
indicates whether the processor is in the Secure state. The possible values of this bit are:
0 the processor is in the Secure state
1 the processor is in the Non-secure state.
If the processor does not implement Security Extensions, this bit is RAZ.
SPNIDdis, bit [17], v6.1 Debug and v7 Debug
Secure Privileged Non-Invasive Debug Disabled bit. The behavior of this bit depends on the
version of the Debug architecture:
v6.1 Debug
If the processor implements Security Extensions, this bit takes the value of the
inverse of the SPNIDEN input. Otherwise it is RAZ.
v7 Debug This bit is the inverse of bit [6] of the Authentication Status Register, see
Authentication Status Register (DBGAUTHSTATUS) on page C10-96.
SPIDdis, bit [16], v6.1 Debug and v7 Debug
Secure Privileged Invasive Debug Disabled bit. The behavior of this bit depends on the
version of the Debug architecture:
v6.1 Debug
If the processor implements Security Extensions, this bit takes the value of the
inverse of the SPIDEN input. Otherwise it is RAZ.
v7 Debug This bit is the inverse of bit [4] of the Authentication Status Register, see
Authentication Status Register (DBGAUTHSTATUS) on page C10-96.
Bits [19:16], v6 Debug only
Reserved, UNK/SBZP.
MDBGen, bit [15]
Monitor debug-mode enable bit. The possible values of this bit are:
0 Monitor debug-mode disabled
1 Monitor debug-mode enabled.
C10-14 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B