ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Some of these registers form part of the CPUID scheme and are described in Chapter B5 The CPUID
Identification Scheme. The other ARMv7 registers are described in either or both of:
CP15 registers for a VMSA implementation on page B3-64
CP15 registers for a PMSA implementation on page B4-22.
Table C10-21 shows where each register is described
Table C10-21 Index to descriptions of the processor Identification registers
Register Description, VMSA Description, PMSA
Main ID Register c0, Main ID Register (MIDR) on
page B3-81
Cache Type Register c0, Cache Type Register (CTR) on
page B3-83
TCM Type Register c0, TCM Type Register (TCMTR)
on page B3-85
TLB Type Register c0, TLB Type Register (TLBTR) on
page B3-86
MPU Type Register PMSA only. Alias of Main ID
Register.
Multiprocessor Affinity Register c0, Multiprocessor Affinity Register
(MPIDR) on page B3-87
Processor Feature Register 0
Processor Feature Register 1
c0, Main ID Register (MIDR) on
page B4-32
c0, Cache Type Register (CTR) on
page B4-34
c0, TCM Type Register (TCMTR)
on page B4-35
VMSA only. Alias of Main ID
Register.
c0, MPU Type Register (MPUIR)
on page B4-36
c0, Multiprocessor Affinity Register
(MPIDR) on page B4-37
CP15 c0, Processor Feature registers on page B5-4
Debug Feature Register 0 c0, Debug Feature Register 0 (ID_DFR0) on page B5-6
Auxiliary Feature Register 0 c0, Auxiliary Feature Register 0 (ID_AFR0) on page B5-8
Memory Model Feature Register 0 to
Memory Model Feature Register 3
Instruction Set Attribute Register 0 to
Instruction Set Attribute Register 5
CP15 c0, Memory Model Feature registers on page B5-9
CP15 c0, Instruction Set Attribute registers on page B5-19
C10-90 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B