ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The formats of the ADFSR and AIFSR are IMPLEMENTATION DEFINED.
Accessing the ADFSR and AIFSR
Protected Memory System Architecture (PMSA)
To access the ADFSR or AIFSR you read or write the CP15 registers with set to 0, set to c5,
set to c1, and set to:
0 for the ADFSR
1 for the AIFSR.
For example:
MRC p15,0,,c5,c1,0 ; Read CP15 Auxiliary Data Fault Status Register
MCR p15,0,,c5,c1,0 ; Write CP15 Auxiliary Data Fault Status Register
MRC p15,0,,c5,c1,1 ; Read CP15 Auxiliary Instruction Fault Status Register
MCR p15,0,,c5,c1,1 ; Write CP15 Auxiliary Instruction Fault Status Register
B4.6.23 CP15 c6, Fault Address registers
There are two Fault Address registers, in CP15 c6, as shown in Figure B4-7 on page B4-54. The two Fault
Address registers complement the Fault Status registers, and are shown in Table B4-17.
Register name Description
Data Fault Address Register (DFAR) c6, Data Fault Address Register (DFAR)
Note
Before ARMv7:
The DFAR was called the Fault Address Register (FAR).
The Watchpoint Fault Address Register (DBGWFAR) was implemented in CP15 c6 with ==1.
From ARMv7, the DBGWFAR is only implemented as a CP14 debug register, see Watchpoint Fault
Address Register (DBGWFAR) on page C10-28.
Fault information is returned using the fault address registers and the fault status registers described in CP15
c5, Fault status registers on page B4-54. For details of how these registers are used see Fault Status and
Fault Address registers in a PMSA implementation on page B4-18.
c6, Data Fault Address Register (DFAR)
Table B4-17 Fault address registers
Instruction Fault Address Register (IFAR) c6, Instruction Fault Address Register (IFAR) on page B4-58
The Data Fault Address Register, DFAR, holds the faulting address that caused a synchronous Data Abort
exception.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-57