ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug State
For more information about the ARMv7 cache maintenance operations, see:
CP15 c7, Cache and branch predictor maintenance functions on page B3-126 for a VMSA
implementation
CP15 c7, Cache and branch predictor maintenance functions on page B4-68 for a PMSA
implementation.
In v6 Debug and on any processor that does not implement Security Extensions, or when debugging in a
state and mode where privileged CP15 operations can be executed, the debugger can use any CP15
operations. These include, but are not limited to, those operations listed in Table C5-5 on page C5-25.
v7 Debug restrictions on instruction cache invalidation in Secure User debug
An ARMv7 implementation that includes the Security Extensions and supports Secure User halting debug
must support Secure User debug access to at least one of these instruction cache invalidation operations:
Invalidate entire instruction cache, and flush branch predictor arrays, MCR p15,0,,c7,c5,0
Invalidate instruction cache by MVA, MCR p15,0,,c7,c5,1.
An implementation might support both of these operations.
If the DSCCR.nWT bit is not implemented, the implementation must also support Secure User debug access
to at least the operation to Clean data or unified cache line by MVA to point of coherency.
A debugger requires access to an instruction cache invalidation operations so that it can maintain coherency
between instruction memory and data memory, and between processors in a multiprocessor system.
However, the architecture imposes restrictions on the operation of these instructions in Debug state, that are
not required when the instructions are used in normal operation. In Secure User mode in Debug state when
invasive debug is not permitted in Secure privileged modes:
If the Invalidate all instruction caches operation is supported it must:
— invalidate all unlocked lines in the cache
— leave any locked lines in the cache unchanged.
If there are locked lines in the cache the instruction can abort, but only after it has invalidated all
unlocked lines. However, there is no requirement for the operation to abort if there are locked lines.
If the Invalidate instruction caches by MVA operation is supported, this operation must not invalidate
a locked line. If an instruction attempts to invalidate a locked line in Secure User mode debug the
implementation must either:
— ignore the instruction
— abort the instruction.
These requirements mean that these instructions might operate differently in Debug state to how they
operate in Non-debug state.
Note
In ARMv7, it is IMPLEMENTATION DEFINED whether instruction cache locking is supported.
C5-26 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B