ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Bit [15] RAZ/SBZP.
RR, bit [14] Round Robin bit. If the cache implementation supports the use of an alternative replacement
strategy that has a more easily predictable worst-case performance, this bit selects it:
0 Normal replacement strategy, for example, random replacement
1 Predictable strategy, for example, round-robin replacement.
When the Security Extensions are implemented, this bit is common to the Secure and
Non-secure versions of the register.
This bit is:
a read/write bit if the Security Extensions are not implemented
if the Security Extensions are implemented:
— a read/write bit if the processor is in Secure state
— a read-only bit if the processor is in Non-secure state.
The replacement strategy associated with each value of the RR bit is IMPLEMENTATION
DEFINED.
If the implementation does not support multiple IMPLEMENTATION DEFINED replacement
strategies this bit is RAZ/WI.
V, bit [13] Vectors bit. This bit selects the base address of the exception vectors:
0 Normal exception vectors, base address 0x00000000.
When the Security Extensions are implemented this base address can be
re-mapped.
1 High exception vectors (Hivecs), base address 0xFFFF0000.
This base address is never remapped.
When the Security Extensions are implemented, this bit is banked between the Secure and
Non-secure versions of the register.
An implementation can include a configuration input signal that determines the reset value
of the V bit. If there is no configuration input signal to determine the reset value of this bit
then it resets to 0.
For more information, see Exception vectors and the exception base address on page B1-30.
I, bit [12] Instruction cache enable bit: This is a global enable bit for instruction caches:
0 Instruction caches disabled
1 Instruction caches enabled.
When the Security Extensions are implemented, this bit is banked between the Secure and
Non-secure versions of the register.
If the system does not implement any instruction caches that can be accessed by the
processor, at any level of the memory hierarchy, this bit is RAZ/WI.
If the system implements any instruction caches that can be accessed by the processor then
it must be possible to disable them by setting this bit to 0.
Cache enabling and disabling on page B2-8 describes the effect of enabling the caches.
B3-100 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B