ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Permitted IMPLEMENTATION DEFINED limits
Debug Registers Reference
The DBGDSCCR is required. However, there can be IMPLEMENTATION DEFINED limits on its behavior.
Table C10-17 lists some examples of possible options for implementations.
Table C10-17 Permitted IMPLEMENTATION DEFINED limits on DBGDSCCR behavior
Limit Description Notes
Full DBGDSCCR Bits [2:0]
implemented
No Write-Back
support
No
Write-Through
support
No I-cache
control
Bit [2] is RAZ/WI -
Interaction with Cache Behavior Override Register
-
Bit [2] is RAZ/WI Force Write-Through feature not supported.
If Secure User halting debug is supported the implementation must
provide cache clean operations in Debug state, see Access to specific
cache management functions in Debug state on page C5-25.
Bit [1] is RAZ/WI Instruction cache linefill and eviction disable features not
implemented.
Instruction fetches are disabled in Debug state. For most
implementations no instruction cache accesses take place in Debug
state, and nIL is not required.
Unified cache Bit [1] is RAZ/WI -
Cache evictions
always enabled
- nIL and nDL disable cache linefills in Debug state. However cache
evictions might still take place even when these control bits are set
to 0.
No linefill control Bits [1:0] are RAZ/WI No cache linefill and eviction disable features are implemented.
An IMPLEMENTATION DEFINED Cache Behavior Override Register (CBOR) might also be implemented in
CP15.
Table C10-18 on page C10-84 shows, for a processor that implements both the Debug state Cache Control
Register (DBGDSCCR) and the CBOR, the relative precedence of the CBOR and the DBGDSCCR
according to the state of the processor.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-83