ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

RSize, bits [5:1]
Protected Memory System Architecture (PMSA)
Region Size field. Indicates the size of the current memory region:
A value of 0 is not permitted, this value is reserved and UNPREDICTABLE.
If N is the value in this field, the region size is 2 N+1 bytes.
En, bit [0] Enable bit for the region:
0 Region is disabled
1 Region is enabled.
Because this register resets to zero, all memory regions are disabled on reset.
All memory regions must be enabled before they are used.
The minimum region size supported is IMPLEMENTATION DEFINED, but if the memory system
implementation includes a cache, ARM strongly recommends that the minimum region size is a multiple of
the cache line length. This prevents cache attributes changing mid-way through a cache line.
Behavior is UNPREDICTABLE if you:
write a region size that is outside the range supported by the implementation
access this register when the RGNR does not point to a valid region in the MPU Data or Unified
address map.
Accessing the DRSR
To access the DRSR you read or write the CP15 registers with set to 0, set to c6, set to
c1, and set to 2. For example:
MRC p15,0,,c6,c1,2 ; Read CP15 Data Region Size and Enable Register
MCR p15,0,,c6,c1,2 ; Write CP15 Data Region Size and Enable Register
c6, Instruction Region Size and Enable Register (IRSR)
The Instruction Region Size and Enable Register, IRSR, indicates the size of the current memory region in
the instruction address map, and to enable or disable:
the entire region
each of the eight subregions, if the region is enabled.
The current memory region is selected by the value held in the RGNR, see c6, MPU Region Number
Register (RGNR) on page B4-66.
The IRSR:
is a 32-bit read/write register
is accessible only in privileged modes
has a defined reset value of 0.
is implemented only when the PMSA implements separate instruction and data memory maps.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-63