ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
B1.8 Advanced SIMD and floating-point support
Advanced SIMD and VFP extensions on page A2-20 introduces:
the VFP extension, used for scalar floating-point operations
the Advanced SIMD extension, used for integer and floating-point vector operations
the Advanced SIMD and VFP extension registers D0 - D31 and their alternative views as S0 - S31
and Q0 - Q15
the Floating-Point Status and Control Register (FPSCR).
For more information about the system registers for the Advanced SIMD and VFP extensions see Advanced
SIMD and VFP extension system registers on page B1-66.
Software can interrogate the registers described in Advanced SIMD and VFP feature identification registers
on page B5-34 to discover the Advanced SIMD and floating-point support implemented in a system.
This section gives more information about the Advanced SIMD and VFP extensions, in the subsections:
Enabling Advanced SIMD and floating-point support
Advanced SIMD and VFP extension system registers on page B1-66
The Floating-Point Exception Register (FPEXC) on page B1-68
Context switching with the Advanced SIMD and VFP extensions on page B1-69
VFP support code on page B1-70
VFP subarchitecture support on page B1-72.
B1.8.1 Enabling Advanced SIMD and floating-point support
If an ARMv7 implementation includes support for any Advanced SIMD or VFP features then the boot
software for any system that uses that implementation must ensure that:
access to CP10 and CP11 is enabled in the Coprocessor Access Control Register, see:
— c1, Coprocessor Access Control Register (CPACR) on page B3-104 for a VMSA
implementation
— c1, Coprocessor Access Control Register (CPACR) on page B4-51 for a PMSA
implementation.
if the Security Extensions are implemented and Non-secure access to the Advanced SIMD or VFP
features is required, the access flags for CP10 and CP11 in the NSACR must be set to 1, see c1,
Non-Secure Access Control Register (NSACR) on page B3-110.
If this is not done, operation of Advanced SIMD and VFP features is UNDEFINED.
If the access control bits are programmed differently for CP10 and CP11, operation of Advanced SIMD and
VFP features is UNPREDICTABLE.
In addition, software must set the FPEXC.EN bit to 1 to enable most Advanced SIMD and VFP operations,
see The Floating-Point Exception Register (FPEXC) on page B1-68.
B1-64 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B