ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
Programmers’ model, bits [3:0]
Support for the standard programmers’ model for ARMv4 and later. Model must support
User, FIQ, IRQ, Supervisor, Abort, Undefined and System modes. Permitted values are:
0b0000 Not supported.
0b0001 Supported.
Accessing the Processor Feature registers
To access the Processor Feature Registers you read the CP15 registers with set to 0, set to c0,
set to c1, and set to:
0 for ID_PFR0
1 for ID_PFR1.
For example:
MRC p15, 0, , c0, c1, 0 ; Read Processor Feature Register 0
B5.2.2 c0, Debug Feature Register 0 (ID_DFR0)
The Debug Feature Register 0, ID_DFR0, provides top level information about the debug system for the
processor. You can obtain more information from the debug infrastructure, see Debug identification
registers on page C10-3.
The format of the ID_DFR0 is:
31 24 23 20 19 16 15 12 11 8 7 4 3 0
Reserved, RAZ
Debug model, M profile
Memory-mapped trace model
Coprocessor trace model
Memory-mapped debug model, A and R profiles
Coprocessor Secure debug model, A profile only
Coprocessor debug model, A and R profiles
Bits [31:24] Reserved, RAZ.
Debug model, M profile, bits [23:20]
Support for memory-mapped debug model for M profile processors. Permitted values are:
0b0000 Not supported.
0b0001 Support for M profile Debug architecture, with memory-mapped access.
B5-6 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B