ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Thumb Instruction Set Encoding
A6.2.4 Load/store single data item
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opA opB
These instructions have one of the following values in opA:
0b0101
0b011x
0b100x.
Table A6-5 shows the allocation of encodings in this space.
All these instructions are available since the Thumb instruction set was introduced in ARMv4T.
opA opB Instruction See
Table A6-5 16-bit Thumb Load/store instructions
0101 000 Store Register STR (register) on page A8-386
001 Store Register Halfword STRH (register) on page A8-412
010 Store Register Byte STRB (register) on page A8-392
011 Load Register Signed Byte LDRSB (register) on page A8-164
100 Load Register LDR (register) on page A8-124
101 Load Register Halfword LDRH (register) on page A8-156
110 Load Register Byte LDRB (register) on page A8-132
111 Load Register Signed Halfword LDRSH (register) on page A8-172
0110 0xx Store Register STR (immediate, Thumb) on page A8-382
1xx Load Register LDR (immediate, Thumb) on page A8-118
0111 0xx Store Register Byte STRB (immediate, Thumb) on page A8-388
1xx Load Register Byte LDRB (immediate, Thumb) on page A8-126
1000 0xx Store Register Halfword STRH (immediate, Thumb) on page A8-408
1xx Load Register Halfword LDRH (immediate, Thumb) on page A8-150
1001 0xx Store Register SP relative STR (immediate, Thumb) on page A8-382
1xx Load Register SP relative LDR (immediate, Thumb) on page A8-118
A6-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B