ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
where:
See Standard assembler syntax fields on page A8-7.
Must be one of:
MLA op = 1
MLS op = 0.
Instruction Details
VN.F64 , , Encoding T1 / A1 with sz = 1
VN.F32 , , Encoding T1 / A1 with sz = 0
VNMUL.F64 {,} , Encoding T2 / A2 with sz = 1
VNMUL.F32 {,} , Encoding T2 / A2 with sz = 0
, , The destination register and the operand registers, for a double-precision operation.
, , The destination register and the operand registers, for a single-precision operation.
Operation
enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL};
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
if dp_operation then
product = FPMul(D[n], D[m], TRUE);
case type of
when VFPNegMul_VNMLA D[d] = FPAdd(FPNeg(D[d]), FPNeg(product), TRUE);
when VFPNegMul_VNMLS D[d] = FPAdd(FPNeg(D[d]), product, TRUE);
when VFPNegMul_VNMUL D[d] = FPNeg(product);
else
product = FPMul(S[n], S[m], TRUE);
case type of
when VFPNegMul_VNMLA S[d] = FPAdd(FPNeg(S[d]), FPNeg(product), TRUE);
when VFPNegMul_VNMLS S[d] = FPAdd(FPNeg(S[d]), product, TRUE);
when VFPNegMul_VNMUL S[d] = FPNeg(product);
Exceptions
Undefined Instruction.
Floating-point exceptions: Invalid Operation, Overflow, Underflow, Inexact, Input Denormal.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-675