ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Memory Model
The second part of the definition of Group B is recursive. Ultimately, membership of Group B derives
from the observation by any observer of an access by Pe that is a member of Group B as a result of
the first part of the definition of Group B.
DMB only affects memory accesses. It has no effect on the ordering of any other instructions executing on the
processor.
For details of the DMB instruction in the Thumb and ARM instruction sets see DMB on page A8-90.
Data Synchronization Barrier (DSB)
The DSB instruction is a special memory barrier, that synchronizes the execution stream with memory
accesses. The DSB instruction takes the required shareability domain and required access types as arguments.
If the required shareability is Full system then the operation applies to all observers within the system.
A DSB behaves as a DMB with the same arguments, and also has the additional properties defined here.
A DSB completes when both:
all explicit memory accesses that are observed by Pe before the DSB is executed, are of the required
access types, and are from observers in the same required shareability domain as Pe, are complete for
the set of observers in the required shareability domain
all cache, branch predictor, and TLB maintenance operations issued by Pe before the DSB are complete
for the required shareability domain.
In addition, no instruction that appears in program order after the DSB instruction can execute until the DSB
completes.
For details of the DSB instruction in the Thumb and ARM instruction sets see DSB on page A8-92.
Note
Historically, this operation was referred to as Drain Write Buffer or Data Write Barrier (DWB). From
ARMv6, these names and the use of DWB were deprecated in favor of the new Data Synchronization Barrier
name and DSB abbreviation. DSB better reflects the functionality provided from ARMv6, because DSB is
architecturally defined to include all cache, TLB and branch prediction maintenance operations as well as
explicit memory operations.
Instruction Synchronization Barrier (ISB)
An ISB instruction flushes the pipeline in the processor, so that all instructions that come after the ISB
instruction in program order are fetched from cache or memory only after the ISB instruction has completed.
Using an ISB ensures that the effects of context altering operations executed before the ISB are visible to the
instructions fetched after the ISB instruction. Examples of context altering operations that require the
insertion of an ISB instruction to ensure the operations are complete are:
cache, TLB, and branch predictor maintenance operations
changes to the CP14 and CP15 registers.
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