ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A6.3.13 Parallel addition and subtraction, signed
Thumb Instruction Set Encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 0 1 op1 1 1 1 1 0 0 op2
If, in the second halfword of the instruction, bits [15:12] != 0b1111, the instruction is UNDEFINED.
Table A6-24 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
These encodings are all available in ARMv6T2 and above.
Table A6-24 Signed parallel addition and subtraction instructions
op1 op2 Instruction See
001 00 Add 16-bit SADD16 on page A8-296
010 00 Add, Subtract SASX on page A8-300
110 00 Subtract, Add SSAX on page A8-366
101 00 Subtract 16-bit SSUB16 on page A8-368
000 00 Add 8-bit SADD8 on page A8-298
100 00 Subtract 8-bit SSUB8 on page A8-370
Saturating instructions
001 01 Saturating Add 16-bit QADD16 on page A8-252
010 01 Saturating Add, Subtract QASX on page A8-256
110 01 Saturating Subtract, Add QSAX on page A8-262
101 01 Saturating Subtract 16-bit QSUB16 on page A8-266
000 01 Saturating Add 8-bit QADD8 on page A8-254
100 01 Saturating Subtract 8-bit QSUB8 on page A8-268
Halving instructions
001 10 Halving Add 16-bit SHADD16 on page A8-318
010 10 Halving Add, Subtract SHASX on page A8-322
110 10 Halving Subtract, Add SHSAX on page A8-324
101 10 Halving Subtract 16-bit SHSUB16 on page A8-326
000 10 Halving Add 8-bit SHADD8 on page A8-320
100 10 Halving Subtract 8-bit SHSUB8 on page A8-328
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A6-35