ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B4.4 PMSA memory aborts
Protected Memory System Architecture (PMSA)
The mechanisms that cause the ARM processor to take an exception because of a memory access are:
MPU fault The MPU detects an access restriction and signals the processor.
External abort A memory system component other than the MPU signals an illegal or faulting
external memory access.
The exception taken is a Prefetch Abort exception if either of these occurs synchronously on an instruction
fetch, and a Data Abort exception otherwise.
Collectively these mechanisms are called aborts. The different abort mechanisms are described in:
MPU faults
External aborts on page B4-15.
An access that causes an abort is said to be aborted, and uses the Fault Address Registers (FARs) and Fault
Status Registers (FSRs) to record context information. The FARs and FSRs are described in Fault Status
and Fault Address registers in a PMSA implementation on page B4-18.
Also, a debug exception can cause the processor to take a Prefetch Abort exception or a Data Abort
exception, and to update the FARs and FSRs. For details see Chapter C4 Debug Exceptions and Debug event
prioritization on page C3-43.
B4.4.1 MPU faults
The MPU checks the memory accesses required for instruction fetches and for explicit memory accesses:
if an instruction fetch faults it generates a Prefetch Abort exception
if an explicit memory access faults it generates a Data Abort exception.
For more information about Prefetch Abort exceptions and Data Abort exceptions see Exceptions on
page B1-30.
MPU faults are always synchronous. For more information, see Terminology for describing exceptions on
page B1-4.
When the MPU generates an abort for a region of memory, no memory access is made if that region is or
could be marked as Strongly-ordered or Device.
The MPU can generate three types of fault, described in the subsections:
Alignment fault on page B4-14
Background fault on page B4-14
Permission fault on page B4-14.
The MPU fault checking sequence on page B4-15 describes the fault checking sequence.
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