ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

LineSize, bits [2:0]
(Log2(Number of words in cache line)) -2. For example:
Protected Memory System Architecture (PMSA)
For a line length of 4 words: Log2(4) = 2, LineSize entry = 0.
This is the minimum line length.
For a line length of 8 words: Log2(8) = 3, LineSize entry = 1.
Accessing the currently selected CCSIDR
The CSSELR selects a CCSIDR, see c0, Cache Size Selection Register (CSSELR) on page B4-43. To access
the currently-selected CCSIDR you read the CP15 registers with set to 1, set to c0, set
to c0, and set to 0. For example:
MRC p15,1,,c0,c0,0 ; Read current CP15 Cache Size ID Register
Accessing the CCSIDR when the value in CSSELR corresponds to a cache that is not implemented returns
an UNKNOWN value.
B4.6.12 c0, Cache Level ID Register (CLIDR)
The Cache Level ID Register, CLIDR:
identifies the type of cache, or caches, implemented at each level, up to a maximum of eight levels
identifies the Level of Coherency and Level of Unification for the cache hierarchy.
The CLIDR is:
a 32-bit read-only register
accessible only in privileged modes
introduced in ARMv7.
The format of the CLIDR is:
31 30 29 27 26 24 23 21 20 18 17 15 14 12 11 9 8 6 5 3 2 0
0 0 LoUU LoC LoUIS Ctype7 Ctype6 Ctype5 Ctype4 Ctype3 Ctype2 Ctype1
Bits [31:30] RAZ.
LoUU, bits [29:27]
LoC, bits [26:24]
Level of Unification Uniprocessor for the cache hierarchy, see Clean, Invalidate, and Clean
and Invalidate on page B2-11.
Level of Coherency for the cache hierarchy, see Clean, Invalidate, and Clean and Invalidate
on page B2-11.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-41