ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
C10.3.6 Program Counter Sampling Register (DBGPCSR)
The Program Counter Sampling Register, DBGPCSR, enables a debugger to sample the Program Counter
(PC).
DBGPCSR is defined only in the v7 Debug architecture. However, an ARMv6 implementation might
implement DBGPCSR as part of the external debug interface.
In v7 Debug:
It is IMPLEMENTATION DEFINED whether DBGPCSR is:
— not implemented
— implemented as debug register 33, at offset 0x084
— implemented as debug register 40, at offset 0x0A0
— implemented both as debug register 33 and as debug register 40.
When DBGPCSR is implemented both as debug register 33 and as debug register 40, the two register
numbers are aliases of each other.
You can determine whether, or how, DBGPCSR is implemented as follows:
— If DBGDIDR.PCSR_imp is 1, DBGPCSR is implemented as debug register 33. Otherwise,
reads of register 33 return an UNKNOWN value.
— If DBGDIDR.DEVID_imp is 1 and DBGDEVID.PCsample is non-zero, DBGPCSR is
implemented as debug register 40. Otherwise, debug register 40 is reserved.
When implemented, the DBGPCSR is:
a read-only register
when the Security Extensions are implemented, a Common register.
Any read through the Extended CP14 interface of a CP14 register that maps to the DBGPCSR is UNDEFINED
in User mode and UNPREDICTABLE in privileged modes.
ARM deprecates reading a PC sample through register 33 when the DBGPCSR is also implemented as
register 40.
The format of the DBGPCSR is:
31
Program Counter Sample value, bits [31:2]
Program Counter Sample value
Meaning of PC Sample Value
The sampled value of bits [31:2] of the PC. The sampled value is an instruction address plus
an offset that depends on the processor instruction set state. See Memory addresses on
page C3-23 for a definition of the Instruction Virtual Address (IVA) read through the
DBGPCSR.
C10-38 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
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