ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
G.5.2 The exception model
The exception vector offsets and priorities as stated in Offsets from exception base addresses on page B1-31
and Exception priority order on page B1-33 are the same for ARMv6 and ARMv7.
See Exception return on page B1-38 for the definition of exception return instructions.
The ARM abort model
ARMv6 and ARMv7 use a Base Restored Abort Model (BRAM), as defined in The ARM abort model on
page AppxH-20.
Exception entry
Entry to exceptions in ARMv6 is generally as described in the sections:
Reset on page B1-48
Undefined Instruction exception on page B1-49
Supervisor Call (SVC) exception on page B1-52
Secure Monitor Call (SMC) exception on page B1-53
Prefetch Abort exception on page B1-54
Data Abort exception on page B1-55
IRQ exception on page B1-58
FIQ exception on page B1-60.
These ARMv7 descriptions are modified as follows:
pseudocode statements that set registers, bits and fields that do not exist in the ARMv6 architecture
variant are ignored
CPSR.T is set to SCTLR.TE in ARMv6T2, as described by the pseudocode, but to 0 in ARMv6 and
ARMv6K.
Fault reporting
In previous ARM documentation, in descriptions of exceptions associated with memory system faults, the
terms precise and imprecise are used instead of synchronous and asynchronous. For details of the
terminology used to describe exceptions in ARMv7, see Terminology for describing exceptions on
page B1-4.
ARMv6 only supports synchronous reporting of external aborts on instruction fetches and translation table
walks. In ARMv7, these faults can be reported as synchronous or asynchronous aborts. Asynchronous
aborts are always reported as Data Abort exceptions.
AppxG-18 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B