ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
This field must be programmed to 0b00000 if either:
DBGWCR[12:5] != 0b11111111, if an 8-bit Byte address select field is implemented
DBGWCR[8:5] != 0b1111, if a 4-bit Byte address select field is implemented.
If this is not done, the generation of Watchpoint debug events is UNPREDICTABLE.
If this field is not zero, the DBGWVR bits that are not included in the comparison must be
zero, otherwise the generation of Watchpoint debug events is UNPREDICTABLE.
To watch for a write to any byte in an doubleword-aligned object of size 8 bytes, ARM
recommends that debuggers set DBGWCR[28:24] = 0x7, and
DBGWCR[12:5] = 0b11111111. This setting is compatible with both implementations with
an 8-bit Byte address select field and implementations with a 4-bit Byte address select field,
because implementations with a 4-bit Byte address select field ignore writes to
DBGWCR[12:9].
Bits [28:24], v6 Debug and v6.1 Debug
Reserved, UNK/SBZP.
Enable linking, bit [20]
This bit is set to 1 if this WRP is linked to a BRP to set a linked watchpoint that requires
both DVA and Context ID comparison. The possible values of this bit are
0 linking disabled
1 linking enabled.
When this bit is set to 1 the Linked BRP number field indicates the BRP to which this WRP
is linked. For more information, see Linked comparisons on page C10-59.
Linked BRP number, bits [19:16]
If this WRP is programmed with linking enabled then this field must be programmed with
the number of the BRP that holds the Context ID to be used for the combined DVA and
Context ID comparison, otherwise, this field must be programmed to 0b0000.
If this field is programmed with a value other than zero or the number of a BRP that supports
Context ID comparison then reading this register returns an UNKNOWN value for this field.
The generation of Watchpoint debug events is UNPREDICTABLE if either:
this WRP does not have linking enabled and this field is not programmed to 0b0000
this WRP has linking enabled and the BRP indicated by this field does not support
Context ID comparison or is not programmed for Linked Context ID match.
Security state control, bits [15:14], when the Security Extensions are implemented
Note
The Security Extensions cannot be implemented with v6 Debug.
When a processor implements the Security Extensions, these bits enable the breakpoint to
be conditional on the security state of the processor:
0b00 watchpoint generated on match in both Non-secure state and Secure state
C10-62 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B