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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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A4.8 Miscellaneous instructions<br />

The Instruction Sets<br />

Table A4-12 summarizes the miscellaneous instructions in the <strong>ARM</strong> <strong>and</strong> Thumb instruction sets.<br />

Instruction See<br />

Clear-Exclusive CLREX on page A8-70<br />

Debug hint DBG on page A8-88<br />

Data Memory Barrier DMB on page A8-90<br />

Data Synchronization Barrier DSB on page A8-92<br />

Instruction Synchronization Barrier ISB on page A8-102<br />

If Then (makes following instructions conditional) IT on page A8-104<br />

No Operation NOP on page A8-222<br />

Table A4-12 Miscellaneous instructions<br />

Preload Data PLD, PLDW (immediate) on page A8-236<br />

PLD (literal) on page A8-238<br />

PLD, PLDW (register) on page A8-240<br />

Preload Instruction PLI (immediate, literal) on page A8-242<br />

PLI (register) on page A8-244<br />

Set Endianness SETEND on page A8-314<br />

Send Event SEV on page A8-316<br />

Supervisor Call SVC (previously SWI) on page A8-430<br />

Swap, Swap Byte. Use deprecated. a<br />

SWP, SWPB on page A8-432<br />

Wait For Event WFE on page A8-808<br />

Wait For Interrupt WFI on page A8-810<br />

Yield YIELD on page A8-812<br />

a. Use Load/Store-Exclusive instructions instead, see Load/store instructions on page A4-19.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A4-23

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