ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Programmers’ Model
application level registers and any additional configuration registers are initialized as required by the
subarchitecture of the implementation.
Executing BXJ with Jazelle extension enabled
Executing a BXJ instruction when the JMCR.JE bit is 1, see Jazelle Main Configuration Register (JMCR) on
page A2-77, causes the Jazelle hardware to do one of the following:
enter Jazelle state and start executing bytecodes directly from a SUBARCHITECTURE DEFINED address
branch to a SUBARCHITECTURE DEFINED handler.
Which of these occurs is SUBARCHITECTURE DEFINED.
The Jazelle subarchitecture can use Application Level registers (but not System Level registers) to transfer
information between the Jazelle extension and the EJVM. There are SUBARCHITECTURE DEFINED
restrictions on what Application Level registers must contain when a BXJ instruction is executed, and
Application Level registers have SUBARCHITECTURE DEFINED values when Jazelle state execution ends and
ARM or Thumb state execution resumes.
Jazelle subarchitectures and implementations must not use any unallocated bits in Application Level
registers such as the CPSR or FPSCR. All such bits are reserved for future expansion of the ARM
architecture.
Executing BXJ with Jazelle extension disabled
If a BXJ instruction is executed when the JMCR.JE bit is 0, it is executed identically to a BX instruction with
the same register operand.
This means that BXJ instructions can be executed freely when the JMCR.JE bit is 0. In particular, if an EJVM
determines that it is executing on a processor whose Jazelle extension implementation is trivial or uses an
incompatible subarchitecture, it can set JE == 0 and execute correctly. In this case it executes without the
benefit of any Jazelle hardware acceleration that might be present.
Application level configuration and control of the Jazelle extension
All registers associated with the Jazelle extension are implemented in coprocessor space as part of
coprocessor 14 (CP14). The registers are accessed using the instructions:
MCR, see MCR, MCR2 on page A8-186
MRC, see MRC, MRC2 on page A8-202.
In a non-trivial implementation at least three registers are required. These are described in:
Jazelle ID Register (JIDR) on page A2-76
Jazelle Main Configuration Register (JMCR) on page A2-77
Jazelle OS Control Register (JOSCR) on page B1-77.
Additional configuration registers might be provided and are SUBARCHITECTURE DEFINED.
The following rules apply to all Jazelle extension control and configuration registers:
All configuration registers are accessed by CP14 MRC and MCR instructions with set to 7.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A2-75