ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VCVT.. , , # Encoded as Q = 1
VCVT.. , , # Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM Advanced SIMD VCVT
instruction must be unconditional.
.. The data types for the elements of the vectors. They must be one of:
.S32.F32 encoded as op = 1, U = 0
.U32.F32 encoded as op = 1, U = 1
.F32.S32 encoded as op = 0, U = 0
.F32.U32 encoded as op = 0, U = 1.
, The destination vector and the operand vector, for a quadword operation.
, The destination vector and the operand vector, for a doubleword operation.
The number of fraction bits in the fixed point number, in the range 1 to 32:
Operation
(64 - ) is encoded in imm6.
An assembler can permit an value of 0. This is encoded as floating-point to integer
or integer to floating-point instruction, see VCVT (between floating-point and integer,
Advanced SIMD) on page A8-576.
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
op = Elem[D[m+r],e,esize];
if to_fixed then
result = FPToFixed(op, esize, frac_bits, unsigned, round_zero, FALSE);
else
result = FixedToFP(op, esize, frac_bits, unsigned, round_nearest, FALSE);
Elem[D[d+r],e,esize] = result;
Exceptions
Undefined Instruction.
Floating-point exceptions: Input Denormal, Invalid Operation, and Inexact.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-581