ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
One implementation scheme is to provide inputs DBGSELFADDR[31:12] and DBGSELFADDRV that a
system designer must tie-off to the correct value. DBGSELFADDRV must be tied HIGH only if
DBGSELFADDR[31:12] is tied off to a valid value, otherwise DBGSELFADDR[31:12] and
DBGSELFADDRV must be tied LOW.
The format of the DBGDSAR is:
31 12 11
DBGSELFADDR[31:12]
This register format applies regardless of the implementation scheme for identifying the debug self address
offset.
DBGSELFADDR [31:12], bits [31:12]
Bits [31:12] of the two’s complement offset from the ROM Table physical address to the
physical address where the debug registers are mapped. Bits [11:0] of the address are zero.
If the Valid field, bits [1:0], is zero the value of this field is UNKNOWN.
Bits [11:2] Reserved, RAZ.
Reserved, RAZ
2 1 0
Valid
Valid, bits [1:0]
This field indicates whether the debug self address offset is valid. In the recommended
implementation it reflects the value of the DBGSELFADDRV signal, and the permitted
values of this field are:
0b00 DBGSELFADDRV is LOW, offset is not valid
0b11 DBGSELFADDRV is HIGH, offset is valid.
Other values are reserved.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-9