ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.118 PLD (literal)
Preload Data signals the memory system that data memory accesses from a specified address are likely in
the near future. The memory system can respond by taking actions that are expected to speed up the memory
accesses when they do occur, such as pre-loading the cache line containing the specified address into the
data cache. For more information, see Behavior of Preload Data (PLD, PLDW) and Preload Instruction
(PLI) with caches on page B2-7.
Encoding T1 ARMv6T2, ARMv7
PLD
PLD [PC,#-0] Special case
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 U 0 (0) 1 1 1 1 1 1 1 1 1 imm12
imm32 = ZeroExtend(imm12, 32); add = (U == ‘1’);
Encoding A1
PLD
ARMv5TE*, ARMv6*, ARMv7
PLD [PC,#-0] Special case
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 1 U (1) 0 1 1 1 1 1 (1)(1)(1)(1) imm12
imm32 = ZeroExtend(imm12, 32); add = (U == ‘1’);
A8-238 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B