ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
SCR bits
AW EA
Table B1-9 shows the possible values for the SCR.AW and SCR.EA bits, and the abort handling that results
in each case:
Effect on abort handling
Table B1-9 Effect of the SCR.AW and SCR.EA bits on abort handling
0 0 All aborts are handled locally using Abort mode. Asynchronous aborts are maskable only in Secure
state.
This is the reset state and supports legacy systems.
0 1 All external aborts, synchronous and asynchronous, are handled in Monitor mode. Asynchronous
aborts are maskable only in Secure state.
All security aborts from peripherals can be treated in a safe manner in Monitor mode.
1 0 All aborts are handled locally, using Abort mode. Asynchronous aborts are maskable in both Secure
and Non-secure states.
1 1 All external aborts are trapped to Monitor mode. Non-secure state can hide asynchronous external
aborts from the Monitor, by changing the CPSR.A bit.
When the SCR.EA bit is set to 1, and an external abort causes entry to Monitor mode, fault information is
written to the Secure copies of the Fault Status and Fault Address registers.
Control of FIQs by the Security Extensions
The CPSR.F bit can be used to disable FIQs. When the Security Extensions are implemented:
the SCR.FW bit controls whether the CPSR.F bit can be modified in Non-secure state
the SCR.FIQ bit controls whether FIQs are handled in FIQ mode or Monitor mode.
For details of these bits see c1, Secure Configuration Register (SCR) on page B3-106.
Table B1-10 on page B1-43 shows the effect of these bits on FIQ handling:
B1-42 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B